Volantis Inc. said it has closed an $88 million funding round to advance a chip architecture designed for AI inference. The Series A was led by angel investor Lachy Groom and Abstract Ventures, the company announced. More than a half-dozen other backers joined the deal.
The investor group includes John Doerr, chair of Kleiner Perkins, and Naveen Rao, who previously led Intel's artificial intelligence products group. Volantis' founding team also brings chip industry experience, with engineers who have worked at Nvidia Corp. and Broadcom Inc. Among their technical achievements is the first commercial implementation of CoWoS, an interconnect widely used in graphics processing units.
Volantis is developing an inference-optimized chip architecture built around a custom memory interconnect. The company says the technology delivers more than 30 times the memory bandwidth of current accelerators. Memory bandwidth, which measures how quickly data moves between a GPU's processing cores and its high-bandwidth memory, is a major factor in AI model performance, since more bandwidth allows faster inference.
The most direct way to raise a GPU's memory bandwidth is to add memory modules, but the wires connecting those modules to processing cores are up to five millimeters long, limiting how many modules fit on a chip. Volantis' interconnect wires reach more than 200 millimeters, according to the company, which it says allows an AI accelerator to carry more than 220 memory chiplets.
The interconnects use an optical design that transmits data as light, generated by microscopic devices called VCSELs. Each VCSEL has three main parts: a quantum well and two mirrors. The quantum well converts some of the electricity running through the host chip into light, and the mirrors amplify it.
VCSELs are easier and often cheaper to manufacture than the lasers typically used in optical networking gear. They can also be made from gallium arsenide, a compound more readily available than the materials most commonly used for miniature lasers.
Volantis plans to ship its chips with a data center inference appliance called the A-1. The system is roughly one-third the size of a standard server rack and offers 10 terabytes of memory with 250 terabits per second of memory bandwidth, according to the company. Volantis estimates it will process up to 10,000 tokens per second on a model with 20 trillion parameters.
Co-founder and Chief Executive Officer Tapa Ghosh wrote in a blog post that the system would enable real-time frontier inference and place entire code bases within context windows. He offered the example of a coding agent finishing a task in 30 seconds instead of 30 minutes.
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