Sipeed reveals Chinese-made DGX Spark and Ryzen AI Halo rival, expected to cost $3,999

Sipeed has unveiled the MaixStation, a compact AI computer built around Chinese-made silicon that the company claims can outperform Nvidia's DGX Spark on some local LLM workloads. The system runs on Axera's AX8860P, a 16-core Arm Cortex-A55 chip with an in-house NPU rated at 256 TOPS at native FP4 with no sparsity, produced on a 6nm process. Sipeed teased the product on its X account with a photo from the AX8860P's announcement at an industrial fair in Shanghai on Tuesday. The company says the MaixStation is expected to cost $3,999.

Sipeed's performance claims have shifted between communications. In one message, the company said the MaixStation is 25% faster on prefill and 30% faster on decode than the DGX Spark running Qwen 27B from a single node, and it later said it expects one unit to run Qwen 3.8-27B. In an email, Sipeed put the gap at about 10% ahead on both prefill and decode versus the DGX Spark, with FP4 enabled on each machine and speculative decoding off, adding that newer runs with a wider lead are not yet official.

The comparison targets are established small AI systems. Nvidia's DGX Spark comes in a 128GB model at 273 GB/s and a 64GB SKU, priced at $6,950 and from $4,999, with the former on sale since October 2025 at its current price since Oct. 2 and the latter expected through partners on Oct. 23. AMD's Ryzen AI Halo includes a 192GB Max+ PRO 495 model at 273 GB/s, released earlier this week at $7,299.99 for the Linux version, and a 128GB Max+ 395 model with 256 GB/s at $3,999.99. All use 256-bit LPDDR5X, leaving memory capacity, compute and software as the main differences.

Memory prices shape these systems' costs. The best U.S. price for a 128GB DDR5 kit was $3,399 in August, and TrendForce expects conventional DRAM contract prices to rise another 10 to 15% this quarter. Sipeed said it used current DRAM prices rather than stock bought last year, and suggested buyers could supply their own SSD to cut the price, noting the MaixStation takes a standard M.2 2280 drive rather than the Spark's less common 2242.

On software, the Spark ships with DGX OS, Nvidia's build of Ubuntu 24.04 LTS with CUDA and Nvidia's AI stack preinstalled, while AMD validates ROCm, drivers, models and frameworks as a Best-Known Configuration. Neither the Spark nor the PRO 495 ships with Windows yet, though AMD says Windows versions are coming soon, and the Max+ 395 model already offers Windows 11 Pro. Sipeed claims vLLM, SGLang and PyTorch support alongside an upcoming NPU toolchain due at the end of October, with Axera adding ONNX, Hugging Face model formats and an OpenAI-compatible API; the MaixStation ships with Debian 13 and Linux 6.18, and Windows support for the PCIe card will depend on demand.

The AX8860P also offers PCIe 5.0, 64-channel video decode with 16-channel encode, and multiple form factors including a single-slot, four-chip PCIe card capable of up to 512GB of memory, with mini and pocket PC products planned. Like the eight-core AX8850 in Radxa's and M5Stack's M.2 accelerator cards, it pairs Cortex-A55 cores with Axera's NPU, now with twice the cores and up to 128GB of memory instead of 8GB. Two- and four-chip cascades reach a theoretical 512 and 1,024 TOPS at a claimed scaling efficiency of about 80%, and the CPU is small and in-order against the Spark's Cortex-X925 and the Halo's Zen 5.

The box measures about 11 by 11 by 3 cm and draws about 40W in typical use, powered over USB-C, according to Sipeed. Ports include 10G SFP+, USB-C, an M.2 2280 slot for a PCIe 5.0 SSD and an MCIO 8i connector for linking a second unit. Sipeed says the MaixStation supports single, dual and quad node configurations plus a PCIe card mode, using a 256 Gbps C2C connection up to 384 Gbps without an extra switch and up to eight nodes, while Nvidia's datasheet says linking four Sparks requires an external switch.

Sipeed also addressed platform openness, saying its BSP SDK is open and that AI can be used to port any distribution. It has previously sold Axera boards dating back to 2022 using the AX620A, AX650N and AX630C. Asked about the bandwidth behind its performance claims, Sipeed suggested the Spark's specs may be overstated and questioned why the DGX is slow, while acknowledging that the Spark's 1 PFLOP figure relies on sparsity. By the source's math, the decode claim is plausible with a 4-bit 27B model at about 13.5GB, where comparable machines top out near 20 tokens per second, or around 270 GB/s, though prefill remains harder to justify given the Spark's dense rate of about 500 TFLOPS against the AX8860P's 256 TOPS. Axera's current stack uses the Pulsar2 NPU compiler, with version 8.0 on Hugging Face last week, and V7.0 docs already list the AX8860, but there is no operator support list for the chip and neither the ax-llm runtime nor the AXCL host-side PCIe driver lists it yet. Sipeed says the end-of-month release covers AXDSL, a kernel-programming language, plus Pulsar2 source code, with SGLang and vLLM running on a custom backend so Hugging Face models run without conversion. Remote-access test units and a few review units will follow during the Kickstarter campaign, the company said.

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